This invention relates to integrated circuits, and more particularly, to taking into account manufacturing variations to minimize performance variations in integrated circuits.
Due to variations in manufacturing processes, individual integrated circuit dies of the same type do not perform identically. For example, some devices may operate reliably at faster speeds than other devices. Sometimes manufacturers sell parts that perform differently as different parts. With this type of approach, fast parts might, as an example, have a different model designation than slow parts and might be sold at a premium price relative to slow parts.
In an effort to quantify such types of manufacturing variations, test structures are fabricated on the same wafer in which the integrated circuits are formed to characterize the performance of the integrated circuit dies. In one conventional arrangement, the test structures include a relatively dense array of transistors under test. The array of transistors under test, however, are not addressable and do not provide accurate voltage/current sensing capabilities. In another conventional arrangement, the test structures include an addressable array of unit cells. Each unit cell, however, includes a substantial amount of control logic in addition to the transistor under test. As a result, the addressable array has low density and occupies a large portion of valuable wafer area.